| Week | Instructor's schedule (TOPICS) |
|---|---|
| Week 1 | VLSI Design Concepts |
| Week 2 | Processing, Layout, Full-Custom Design |
| Week 3 | Device and Modeling |
| Week 4 | CMOS Logic Design |
| Week 5 | Cadence Schematic &HSPICE Script Generation |
| Week 6 | Cadence Layout Editor – Virtuoso |
| Week 7 | Layout Verifications – DRC、ERC、LVS |
| Week 8 | Layout Verifications -- Dracula |
| Week 9 | 期中考 |
| Week 10 | Advanced CMOS Logic Designs I |
| Week 11 | Latches, FFs, and Synchronous Systems |
| Week 12 | Advanced CMOS Logic Designs II |
| Week 13 | Advanced CMOS Logic Designs III |
| Week 14 | I/O cirucit design |
| Week 15 | introcuction to ESD |
| Week 16 | Memory Design |
| Week 17 | Cell-Based Design Concepts |
| Week 18 | 期末考 |
